The present invention generally relates to semiconductor device and their fabrication. More specifically, the present invention relates to co-integrated fabrication processes and resulting structures for integrating a junction field effect transistors (JFETs) into a vertical field effect transistor (VFET) device architecture.
Field effect transistors (FETs) have been known for a number of years and are now the transistor of choice for use in complex integrated digital circuits. In general, FETs can be fabricated somewhat more simply and with larger process windows than bipolar junction transistors (BJTs) and, additionally, allow simplified circuit and device design. Constraints on transistor footprint size and current-carrying capacity are continually increasing to satisfy demands for higher digital switching performance, increased functionality and economy of manufacture.
In contemporary semiconductor device fabrication processes, a large number of semiconductor devices, such as silicon channel n-type field effect transistors (nFETs) and silicon germanium channel p-type field effect transistors (pFETs), are fabricated on a single wafer. Non-planar transistor device architectures, such as junction field effect transistors (JFETs) and VFETs can provide increased device density and increased performance over planar transistors. JFETs offer large conduction channel that can be used to control the flow of electric current. VFETs offer narrow channel lengths that offer low voltage and rapid response switching.